Why does increasing sensor size necessarily lead to lower silicon wafer utilization?

Question

MichaelT posted an answer to the question "What limits the size of digital imaging sensors?" which included this illustration of why increasing the size of the sensor leads to an increase of wasted silicon wafer area:

However, the "maximum yield" calculation seems wrong here, and as an implication of that, the waste figure as well. There is a lot of silicon that isn't getting used particularly in the "full frame sensor" illustration in the above image.

What is there to stop using the area surrounding the set of larger sensors for smaller ones? Is it just a matter of the process that is currently used, or is there something inherent to the making of digital imaging sensors that makes such a (multiple-sensor-sizes) process impractical? Or is the illustration overly simplified (and thus the numbers misleading), and that's what manufacturers already do?

Answer 1

There is nothing that stops them putting smaller sensors on the wafer. It is rather doable.

Some concerns are:

• Too close to the edge the mechanical processing introduces stress and dislocations so don't consider the entire wafer having the same quality... The best bet is that on the perimeter you will have higher failure count. That is why on your left image they do not even go close to the perimeter with the placement, because they don't want to risk having a faulty sensor of that size.

• Probing happens as soon as possible to avoid costs of further processing of faulty dies. Now if you have two layout versions, you need a specialized probing station, adding to the cost.

• Probing the smaller sensors temporarily stops the processing of the big ones. When you manufacture chips, you want to push them out as soon as possible. It may happen that stalling those big sensors may mean slower manufacture of high-priced end products, meanwhile you will have some smaller sensors, but your financial balance is way negative...

• How are you going to cut those dies? It is not a simple process. You cannot cut around contours... You cut straight lines, that's all. Now, you could theoretically pick the segments that contain the smaller dies and process further, but just touching and handling them adds to the cost. Really.

In general, when you manufacture chips, you want to do it as simple as possible, as fast as possible, with a specified yield (e.g. 99.7% per wafer), with minimal investment.

It's all about value created, ROI, etc. Usually not worth altering the industry-standard flows...

Answer 2

Looking at those images/calculations it seems right to me. You might have enough silicon to make another sensor, but it's not in the right place. There's not another 24mm x 36mm spot anywhere on that wafer to make an additional sensor, hence the waste.

Additionally, you'll get some bad sensors (I once was given an Intel CPU keychain that was from a dud). Increasing the size of the sensor increases the chances that there will be a flaw and you lose that entire 24x36mm space which is proportionately more of the wafer than if you had a dud small sensor.

Answer 3

Firstly, I think this is off topic.

Secondly, I can't directly answer specifically for silicone, but I did work in circuit board manufacture. I assume the same the same points apply.

When preparing the job it costs twice as much to two panel on one board.

When manufacturing board we normally had production set up for one specific board. Switching between jobs costs time and money. If the different boards were on the same panel you still have to switch twice, minimum, in each batch. Where as with a single job you can keep going for multiple batches in a row.

You do not get 100% yeild. Most of the loss is at the edges of the panel. Exactly where the diagrams show the waste space. Then there is how many you require. You have the cost of manufacturing both boards whether you require them or not. This will likely increase wastage.

All in it's unlikely to be cost effective, and requires a lot more effort

Answer 4

For high value chips, like imaging sensors or i7 CPUs, it generally isn't worth it - silicon real estate isn't the major part of the costs.

You would need the other chips to be smaller, but have a similar number of mask layers and the same etch chemistry. It's likely that your smaller sensors are an older design and the processing has evolved.

If you are already mass producing the small sensors then it is probably not worth the handling costs of dicing, mounting and testing a few extra ones from a different wafer run.

But we have had small custom CCDs made for free in the past by putting them in the corner of wafers being used for very expensive science grade CCDs. All we paid for was the mounting.