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MichaelT posted an answer to the question "What limits the size of digital imaging sensors?" which included this illustration of why increasing the size of the sensor leads to an increase of wasted silicon wafer area:

enter image description here

However, the "maximum yield" calculation seems wrong here, and as an implication of that, the waste figure as well. There is a lot of silicon that isn't getting used particularly in the "full frame sensor" illustration in the above image.

What is there to stop using the area surrounding the set of larger sensors for smaller ones? Is it just a matter of the process that is currently used, or is there something inherent to the making of digital imaging sensors that makes such a (multiple-sensor-sizes) process impractical? Or is the illustration overly simplified (and thus the numbers misleading), and that's what manufacturers already do?

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6  
This question could be a better fit for the Electrical Engineering site. However, my best guess is that, while smaller production can see different devices etched on the same wafer, it's not as convenient for mass production where sorting the different "chips" would add complexity to the machinery. –  clabacchio Aug 28 at 11:43
    
Possibly related: stackoverflow.com/questions/14696785/… –  Richard Smith Aug 28 at 11:54
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Possibly related: electronics.stackexchange.com/questions/79874/… which discusses chip yields on silicon which would apply equally to sensors as processors. –  James Snell Aug 28 at 12:30
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Do a google image search for something like "ccd sensor wafer" or similar, and you will find that they actually do it. –  PlasmaHH Aug 28 at 17:03
    
Don't confuse MPW and similar test-chip-type manufacturing with production runs... On MPW, you can have all kind of weird placements, but you have to handle dies separately, and the cost of that is considerable. –  TFuto Aug 29 at 14:33

4 Answers 4

up vote 6 down vote accepted

There is nothing that stops them putting smaller sensors on the wafer. It is rather doable.

Some concerns are:

  • Too close to the edge the mechanical processing introduces stress and dislocations so don't consider the entire wafer having the same quality... The best bet is that on the perimeter you will have higher failure count. That is why on your left image they do not even go close to the perimeter with the placement, because they don't want to risk having a faulty sensor of that size.

  • Probing happens as soon as possible to avoid costs of further processing of faulty dies. Now if you have two layout versions, you need a specialized probing station, adding to the cost.

  • Probing the smaller sensors temporarily stops the processing of the big ones. When you manufacture chips, you want to push them out as soon as possible. It may happen that stalling those big sensors may mean slower manufacture of high-priced end products, meanwhile you will have some smaller sensors, but your financial balance is way negative...

  • How are you going to cut those dies? It is not a simple process. You cannot cut around contours... You cut straight lines, that's all. Now, you could theoretically pick the segments that contain the smaller dies and process further, but just touching and handling them adds to the cost. Really.

In general, when you manufacture chips, you want to do it as simple as possible, as fast as possible, with a specified yield (e.g. 99.7% per wafer), with minimal investment.

It's all about value created, ROI, etc. Usually not worth altering the industry-standard flows...

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Photography seniors are incidentally running counter to the rest of the industry in that we want bigger sensors while the rest of the fabrication industry wants smaller chips (faster clock speeds, higher yields...) thus it poses an interesting anti-economy of anti-scale. –  MichaelT Aug 28 at 20:45
    
@MichaelT: How exactly is sensor fabrication related to chip fabrication? –  Bobby Alexander Aug 29 at 7:57
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@BobbyAlexander - Because sensors are a type of IC, using the same types of processes to fabricate, e.g. Starting with a Silicon boule, slice, polish, lithographic steps, etching steps, deposition, etc. –  B Shaw Aug 29 at 13:01

Looking at those images/calculations it seems right to me. You might have enough silicon to make another sensor, but it's not in the right place. There's not another 24mm x 36mm spot anywhere on that wafer to make an additional sensor, hence the waste.

Additionally, you'll get some bad sensors (I once was given an Intel CPU keychain that was from a dud). Increasing the size of the sensor increases the chances that there will be a flaw and you lose that entire 24x36mm space which is proportionately more of the wafer than if you had a dud small sensor.

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+1. This is the real answer. Yield on a large sensor is probably quite low. For a 12 inch or even 8 inch wafer, the cost of the unused area is a relatively small overhead per sensor. Yield is almost certainly a bigger issue. Imperfections happen randomly, so the larger the chip, the higher chance it will be a dud. –  Olin Lathrop Aug 28 at 14:05
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"There's not another 24mm x 36mm spot anywhere on that wafer to make an additional sensor," Well, that's where the "smaller ones" part of my question comes from. –  Michael Kjörling Aug 28 at 15:11
    
@MichaelKjörling This is probably technically feasible, but procedurally impractical. Given the amount of testing that these things would undergo, any change you wanted to make to one sensor type (even just adding a new one or discontinuing an old one) would result in retesting the entire thing. –  tenmiles Aug 28 at 17:11
    
It wasn't entirely easy picking the answer to this question to accept. I liked both yours and TFuto's, but ended up accepting TFuto's because it gave a handful of concrete reasons, and upvoted this one. This answer would be even better if you incorporated that last comment into the answer itself, IMO. –  Michael Kjörling Aug 29 at 18:55

Firstly, I think this is off topic.

Secondly, I can't directly answer specifically for silicone, but I did work in circuit board manufacture. I assume the same the same points apply.

When preparing the job it costs twice as much to two panel on one board.

When manufacturing board we normally had production set up for one specific board. Switching between jobs costs time and money. If the different boards were on the same panel you still have to switch twice, minimum, in each batch. Where as with a single job you can keep going for multiple batches in a row.

You do not get 100% yeild. Most of the loss is at the edges of the panel. Exactly where the diagrams show the waste space. Then there is how many you require. You have the cost of manufacturing both boards whether you require them or not. This will likely increase wastage.

All in it's unlikely to be cost effective, and requires a lot more effort

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I don't really get it. I can understand why it'd make a difference making a completely different device, but are smaller sensors really that different from larger ones? –  Michael Kjörling Aug 28 at 15:11
    
Iain seems to know a lot more than I do, but from what he's saying I think it's that the overhead is prohibitive. –  Andy Blankertz Aug 28 at 17:42
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If you think the question is off-topic, don't answer it! Flag it for closing or, if you think it's on-topic on some other Stack Exchange, flag it to be migrated there. (I suppose if you flag it for migration, there's no harm in answering it before it's actually moved, since the answer would be moved, too.) –  David Richerby Aug 28 at 21:06

For high value chips, like imaging sensors or i7 CPUs, it generally isn't worth it - silicon real estate isn't the major part of the costs.

You would need the other chips to be smaller, but have a similar number of mask layers and the same etch chemistry. It's likely that your smaller sensors are an older design and the processing has evolved.

If you are already mass producing the small sensors then it is probably not worth the handling costs of dicing, mounting and testing a few extra ones from a different wafer run.

But we have had small custom CCDs made for free in the past by putting them in the corner of wafers being used for very expensive science grade CCDs. All we paid for was the mounting.

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Out of curiosity, who are the "we" in the last paragraph? –  Michael Kjörling Aug 29 at 7:22
    
@MichaelKjörling - university Astronomy dept –  Martin Beckett Aug 29 at 23:58

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